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MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
The MC100EP809 is a low skew 1-to-9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or PECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 8). The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (See Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair (see Figure 7).
http://onsemi.com MARKING DIAGRAM*
MC100 EP809 32-LEAD LQFP FA SUFFIX CASE 873A AWLYYWW 32 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
* 100 ps Typical Device-to-Device Skew * 15 ps Typical Within Device Skew * HSTL Compatible Outputs Drive 50 W to Ground with no Offset * * * Fully Compatible with Micrel SY89809L * PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V * Open Input Default State
with GND = 0 V, VCCO = 1.6 V to 2.0 V Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay
ORDERING INFORMATION
Device MC100EP809FA MC100EP809FAR2 Package LQFP-32 LQFP-32 Shipping 250 Units/Tray 2000/Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
August, 2002 - Rev. 5
Publication Order Number: MC100EP809/D
MC100EP809
VCCO VCCO 17 16 15 14 VCCO Q6 Q6 Q7 Q7 Q8 Q8 VCCO 13 12 11 10 9 1 2 3 4 5 6 7 8 OE CLK_SEL L H L H Q3 Q3 Q4 Q4 Q5 19 LVPECL_CLK Q5 18 OE* L L H H GND
24 VCCO Q2 Q2 Q1 Q1 Q0 Q0 VCCO 25 26 27 28 29 30 31 32
23
22
21
20
MC100EP809
All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO).
Figure 1. 32-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0-Q8, Q0-Q8 VCCI VCCO GND FUNCTION HSTL or LVDS Differential Inputs LVPECL Differential Inputs LVCMOS/LVTTL Input CLK Select LVCMOS/LVTTL Output Enable HSTL Differential Outputs Positive Supply_Core (3.0 V - 3.6 V) Positive Supply_HSTL Outputs (1.6 V - 2.0 V) Ground
LVPECL_CLK
HSTL_CLK
HSTL_CLK
CLK_SEL
VCCI
FUNCTION TABLE
Q0-Q8 L L HSTL_CLK LVPECL_CLK Q0-Q8 H H HSTL_CLK LVPECL_CLK
* The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVPECL_CLK signal.
* Pins will default LOW when left open. ** Pins will default HIGH when left open. CLK_SEL
HSTL_CLK HSTL_CLK LVPECL_CLK VCCI GND LVPECL_CLK
0 9 9 1 Q OE D VCCO Q0-Q8 (HSTL) Q0-Q8 (HSTL)
Figure 2. Logic Diagram http://onsemi.com
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MC100EP809
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 478 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCCI VCCO VI Iout TA Tstg qJA qJC Tsol Parameter Core Power Supply HSTL Output Power Supply PECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Condition 1 GND= 0 V GND= 0 V GND = 0 V Continuous Surge Condition 2 VCCO= 1.8 V VCCI = 3.3 V VI VCCI Rating 4 4 6 50 100 0 to +85 -65 to +150 80 55 12 to 17 265 Units V V V mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0C Symbol ICC VIH VIL VIHCMR Characteristic Core Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 3) (Figure 4) LVPECL_CLK/LVPECL_CLK Input HIGH Current Input LOW Current Min 75 VCCI- 1.165 VCCI- 1.945 Typ 95 Max 115 VCCI -0.88 VCCI -1.6 Min 75 VCCI- 1.165 VCCI- 1.945 25C Typ 95 Max 115 VCCI -0.88 VCCI -1.6 Min 75 VCCI- 1.165 VCCI- 1.945 85C Typ 95 Max 115 VCCI -0.88 VCCI -1.6 Unit mA V V
1.2 -150 -150
VCCI 150 150
1.2 -150 -150
VCCI 150 150
1.2 -150 -150
VCCI 150 150
V mA mA
IIH IIL NOTE:
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP809
LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0C Symbol VIH VIL IIH IIL NOTE: Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current -150 -300 Min 2.0 0.8 150 300 -150 -300 Typ Max Min 2.0 0.8 150 300 -150 -300 25C Typ Max Min 2.0 0.8 150 300 85C Typ Max Unit V V mA mA
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0C Symbol VOH VOL VIH VIL VX IIH IIL VIHCMR Characteristic Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Figure 5) Input LOW Voltage (Figure 5) HSTL Input Crossover Voltage Input HIGH Current Input LOW Current Input HIGH Voltage Common Mode Range (Differential) (Note 5) HSTL_CLK/HSTL_CLK Min 1.0 0.1 VX+0.1 -0.3 0.68 -150 -300 - - - Typ Max 1.2 0.4 1.6 VX-0.1 0.9 150 300 Min 1.0 0.1 VX+0.1 -0.3 0.68 -150 -300 - - - 25C Typ Max 1.2 0.4 1.6 VX-0.1 0.9 150 300 Min 1.0 0.1 VX+0.1 -0.3 0.68 -150 -300 - - - 85C Typ Max 1.2 0.4 1.6 VX-0.1 0.9 150 300 Unit V V V V V mA mA
0.6
VCCI -1.2
0.6
VCCI -1.2
0.6
VCCI -1.2
V V
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. All outputs loaded with 50 W to GND (See Figure 6). 5. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
NOTE:
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MC100EP809
AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 6)
0C Symbol VOpp Characteristic Differential Output Voltage (Figure 3) fout < 100 MHz fout < 500 MHz fout < 750 MHz Min 600 600 450 680 690 Typ 850 750 575 800 830 15 100 1.4 200 200 0.5 0.5 350 600 930 990 50 200 3.0 200 200 0.5 0.5 350 450 600 Max Min 600 600 450 700 700 25C Typ 850 750 575 820 850 15 100 1.4 950 1000 50 200 3.0 200 200 0.5 0.5 350 600 Max Min 600 600 450 780 790 85C Typ 850 750 575 920 950 15 100 1.4 1070 1110 50 200 3.0 Max Unit mV mV ps ps ps ps ps mV mV ns ns ps
tPLH tPHL tskew tJITTER VPP
Propagation Delay (Differential) LVPECL_CLK to Q HSTL_CLK to Q Within-Device Skew (Note 7) Device-to-Device Skew (Note 8) Random Clock Jitter (Figure 3) (RMS) Input Swing (Differential Mode) (Note 10) (Figure 4) LVPECL HSTL OE Set Up Time (Note 9) OE Hold Time Output Rise/Fall Time (20%-80%)
tS tH tr/tf
6. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to Ground (See Figure 6). 7. Skew is measured between outputs under identical transitions and conditions on any one device. 8. Device-to-Device skew for identical transitions and conditions. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High-to-Low transition ensures outputs remain disabled during the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock (See Figure 8). 10. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
900 800 700 VOPP (mV) 600 500 400 300 RMS JITTER 200 100 0 0 100 200 300 400 500 600 700 800 900 VOPP
9 8 7 tJITTER ps (RMS) 6 5 4 3 2 1 1000
FREQUENCY (MHz)
Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
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MC100EP809
VCCI(LVPECL) VIH(DIFF) VPP VIHCMR VIL(DIFF) GND VPP VCCI VCCO(HSTL) VIH(DIFF) VX VIL(DIFF) GND
Figure 4. LVPECL Differential Input Levels
Figure 5. HSTL Differential Input Levels
Q
Z = 50 W
HSTL OUTPUT Q 50 W
50 W GROUND
Figure 6. HSTL Output Termination and AC Test Reference
CLK/CLK D.C. Bias*
*Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2).
Figure 7. HSTL Single-Ended Input Configuration
CLK
CLK
OE
Q
Q
Figure 8. Output Enable (OE) Timing Diagram
Resource Reference of Application Notes
AN1405 AN1406 AND8002 AND8009 AND8020 - - - - - ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP809
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V
AE P AE
DETAIL Y
17
V1
DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
BASE METAL
-AC- 0.10 (0.004) AC
N
F
D
0.20 (0.008)
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
AC T-U Z
-T-, -U-, -Z-
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
8X
M_ R
SECTION AE-AE
CE
X DETAIL AD
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
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EE EE EE
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
MC100EP809
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PUBLICATION ORDERING INFORMATION
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MC100EP809/D

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